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Life beyond CMOS

 

“For the last 40 years computers have been getting faster as CMOS chips have become smaller, faster and cheaper. But all good things come to an end and, all around the world, people have begun looking at alternative electronic devices that might follow on from CMOS.”


So said Dr Michael Forshaw, coordinator of IST project ESCHER, who gathered with other researchers to present recent findings in the search for new technology to succeed CMOS (complementary metal oxide semiconductors), during the 15th Nanotechnology Information Devices (NID) Workshop, organised by the PHANTOMS Network of Excellence.

CMOS has been the dominant chip technology used by the world’s electronics industry for several decades. CMOS semiconductors use both negative and positive polarity circuits. Since only one of the circuit types is on at any given time, CMOS chips require much less power than chips using just one type of transistor. This makes them particularly attractive for use in battery-powered devices, such as portable computers.

Getting smaller
Since their introduction, CMOS transistors have shrunk exponentially in size in accordance with Moore’s Law. This law predicts a doubling of transistors per integrated circuit every 18 months. However, the ability to scale down CMOS further appears to be reaching physical and technical limits. The International Technology Roadmap for Semiconductors (ITRS), a worldwide organisation responsible for identifying the technological challenges and needs facing the semiconductor industry, predicts the size limit for CMOS technology to be 5 to 10 nm. Furthermore, ITRS believes this limit will be reached in 15-20 years time.

Semiconductor industries such as Intel in the US and Infineon, STMicroelectronics and Philips in Europe are now developing the factories for CMOS chips with 65nm size features, the `65 nm node´, which ITRS foresees in full production in 2007. To meet future needs of the electronics industry, ITRS has set semiconductor manufacturers the target of producing 45nm CMOS technology nodes, or junctions, by 2010. However, to manufacture CMOS technology below 65nm, new fabrication treatments are needed. “The problem with conventional thermal treatments,” explained Dr Vittorio Privitera of Consiglio Nazionale delle Ricerche (CNR), “is it is not possible any more to achieve the junction depths and the special characteristics of the dopant layer that are required.”

Privitera is the coordinator of the FLASH project, which has been developing a new laser-based treatment, called excimer laser annealing (ELA), to meet the ITRS target. Initial results have been extremely encouraging. “The laser is able to make ultra-shallow junctions with dopant profiles which are extremely sharp and electrically very active. This is the first time that this has been done,” reported Privitera. Over the course of 2005, Privitera and his partners intend to construct and evaluate a prototype production line for fabricating MOSFET transistors using the new method.

Recently completed project NEAR was also at the workshop. NEAR aimed at developing new non-CMOS nanoelectronic devices that are extremely compact, consume low power and operate at room temperature. Two component types were investigated, known as Three Terminal Ballistic Junction (TBJ) devices and Self Switching Devices (SSD). During the project, basic logic circuits were created using TBJ and SSD devices, and successfully operated at room temperature.


Looking to the future
Discussing future directions in mono-molecular electronics, the name given to digital logic circuits designed using single molecules, Dr Christian Joachim, a Research Director at the Centre National de la Recherche Scientifique (CNRS) and CHIC project partner, described the majority view that: “We have decided to take a bottom-up approach, starting with atoms and asking ourselves ‘what do we need?’ or ‘what is the minimum sized molecule to implant a computation inside it?’” Amongst the key issues to be tackled are: what computing resources are available, how information can be exchanged internally, and what cooling and energy requirements there are.

Another area covered at the event was alternative electronics, investigating devices that could replace CMOS beyond the 10 to 5 nm frontier and provide at least comparable performance whilst requiring less power and lower fabrication costs. Dr Arianna Filoramo, a researcher at CEA-Saclay and SATURN project partner, explained how current research is looking into areas such as the fabrication and characterisation of low dimensional materials such as nanowires, nanotubes and nanodots; new methods of fabricating nanodevices such as self-assembly and molecular lego; as well as new architecture paradigms for nanodevices.

A third strand was nano-electro-mechanical systems (NEMS). Said Professor Jürgen Brugger of Ecole Polytechnique Fédérale de Lausanne (EPFL): “I would like to emphasise the ‘m’ in nano-electro-mechanical systems. We are really focussing on the mechanical aspects of nanodevices.” The identified challenges being tackled included nanoscale mechanics, fabrication techniques for NEMS elements, detection methods and interfacing of NEMS.

The broad spectrum of discussions that took place at the NID Workshop served to show that the semiconductor industry is entering an exciting, if uncertain, period. The expected physical challenges of advancing CMOS technology is creating a flurry of activity which is leading to a wide range of potential technical successors. Technology fragmentation means there will be a tremendous opportunity for the industry to differentiate and so add value, supported by researchers such as those at the NID Workshop.

Contact:
Dr David Guedj
Scientific Officer
Future Emerging Technologies
DG Information Society and Media- F1 (BU33 3/48)
European Commission
B-1049 Brussels
Belgium
Tel: +32-2-2955121
Email: david.guedj@cec.eu.int

Dr Patrick Van Hove
Head of Sector
Future Emerging Technologies
DG Information Society and Media- F1 (BU33 3/11)
European Commission
B-1049 Brussels
Belgium
Tel: +32-2-2968106
Email: patrick.van-hove@cec.eu.int

Source: Based on information from NID workshop

 


 


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