Austin,
TX (9 August, 2005) - SEMATECH engineers have developed
an innovative pore-sealing technique that appears
to prevent metal and precursor penetration into low-k
dielectric materials, easing the introduction of
low-k at the 45 nm technology node.
The potential solution calls for sealing the sponge-like
pores in low-k materials through a chemical vapor
deposition (CVD) sequence that achieves with a
very high degree of conformality with minimal impact
on k-effective. SEMATECH interconnect engineers
Sri Satyanarayana and Eric Busch describe the method
in a technical article appearing in the August
issue of Solid State Technology.
"SEMATECH has long been committed to identifying manufacturable low-k materials
and processes for our members to use in advanced manufacturing," said Sitaram
Arkalgud, the consortium's Interconnect director. "Here we have the basis
of a true solution that will solve the industry's pressing problem of getting
these materials ready for the 45 nm node."
Low-k materials are porous substances that are
much less dense than silicon dioxide, the starting
material for semiconductors, or chips. Low-k
is critical to advanced semiconductor manufacturing
because it allows metal lines to be packed closer
together on a chip with less risk of electrical signal leakage, which can create
interference problems within the chip. Also, low-k must be evaluated in context
of k-effective (keff), which is the overall k-value of a low-k material and
its associated layers.
Throughout the late 1990s and early 2000s, the
semiconductor industry drove relentlessly toward
developing materials with progressively decreasing
k-values, but process induced damage to these
materials is becoming increasingly problematic
as the industry approaches the 45 nm node. SEMATECH's
work in this area supports the industry goal
of obtaining an effective k-value of 2.5 for
the 45 nm node, which is slated to enter production
in 2010.
In the Solid State Technology article, Satyanarayana
and Busch note that pore sealing is critical
to advanced low-k development because conducting
metals such as copper (as well as precursor chemicals
used in conjunction with them) tend to penetrate
low-k materials during CVD or atomic layer deposition
(ALD). Such penetration, which occurs in standard
damascene processing, causes increased current
leakage, heightened capacitance, and degradation
in the reliability of chip structures.
However, SEMATECH's technique alters the damascene
process by applying a commercially available material
through CVD after etching. The material penetrates
the vertical walls of the etched dielectric to
seal the pores, but does not leave an "overburden" of
pore sealant along the sidewalls. The full details of this process are proprietary,
but have been transferred to SEMATECH's member companies and are available on
the consortium's member secure website.
According to the authors, "The new approach provided both pore sealing and
protection from dielectric damage," with no evidence of copper penetration
into the low-k, and significantly less carbon depletion. The process also proved
effective in blocking the precursors for ALD-applied tantalum. (However, further
tests are needed to establish process reliability.)
The authors also predict that the new process could be used for dual-damascene
treatments. "This technique is promising because it not only seals the porous
low-k to avoid barrier and copper penetration, but it also addresses the issue
of low-k damage," Arkalgud said. The full article is available at the Solid
State Technology website, <http://sst.pennnet.com/home.cfm>.
About SEMATECH:
SEMATECH is the world's catalyst for accelerating the commercialization of
technology innovations into manufacturing solutions. By setting global direction,
creating opportunities for flexible collaboration, and conducting strategic
R&D, SEMATECH delivers significant leverage to our semiconductor and
emerging technology partners. In short, we are accelerating the next technology
revolution. For more information, please visit our website at www.sematech.org <http://www.sematech.org>.
SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF,
the ATDF logo, Advanced Technology Development Facility, ISMI and International
SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc.
About Solid State Technology:
Solid State Technology serves engineers and engineering managers all over the
globe in semiconductor/thin film manufacturing, with in-depth, technical
authoritative information on the latest advances in processes and materials
for fabrication of integrated circuits, discretes, and other thin-film devices.
Solid State Technology also covers metrology, robotics/automation/wafer handling,
fab software, yield improvement, contamination control, vacuum technology,
and other allied technologies for semiconductor/thin-film processing plants,
as well as fab management topics. WaferNews is Solid State Technology's weekly
newsletter that is received by executives in the semiconductor equipment
and materials industry. For more information, visit www.solid-state.com <http://www.solid-state.com>
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